Ever higher integration densities are being sought after in integrated semiconductor circuits, leading to reduced feature sizes in the semiconductor material and in particular to reduced feature widths of the electrically conductive structures. Where these electrically conductive structures have hitherto preferably been deposited by means of aluminum layers in corresponding wiring levels to produce interconnects and then patterned by photolithography, conventional methods of this nature can no longer be used for current and future interconnect structures on account of the limited scalability and insufficient migration properties.
Therefore, alternative materials and methods are increasingly being employed, in particular for use in metallization layers of this nature, in order to satisfy the increasing integration density. The use of, for example, copper for wiring levels of this type makes it possible, on account of the significantly improved scalability compared to aluminum, to develop integrated semiconductor circuits which work with a significantly higher current-carrying capacity and at a lower power consumption.
Consequently, what are known as Damascene or dual-Damascene processes, in which a trench in an insulating or dielectric layer is substantially filled with electrically conductive material and is then planarized, resulting in a highly planar electrically conductive structure, are increasingly being used to realize electrically conductive structures with a very small feature size of this nature.
Particularly in the case of a planarization step of this nature, there is a risk of residues in the form of dendrites being formed at metal interconnects, which can lead to functional failures.
FIGS. 1A and 1B show a simplified plan view and a simplified sectional view of a semiconductor circuit arrangement in accordance with the prior art in order to illustrate dendrite formation of this nature during the abovementioned planarization step.
In accordance with FIGS. 1A and 1B, a semiconductor circuit arrangement comprises, for example, a semiconductor substrate 1, which has a first doping region of a first conduction type p. In this first doping region 1, by way of example, a second doping region 2 in the form of an n− doped well is formed, a connection doping region 3 having, for example, an n+ doping being formed at the semiconductor surface for connection of the second doping region 2.
In accordance with FIGS. 1A and 1B, the electrically conductive structure has, for example, an interconnect layer 5 formed in a trench and a contact hole or via 4 filled with electrically conductive material.
During the above-described fabrication of the interconnect layer 5 in the trench, a planarization step is fundamentally required to realize the very fine feature sizes, which usually involves carrying out a chemical mechanical polishing (CMP) step. However, this planarization step may result in an undesired charging of the second doping region or of the well 2, which leads to an excessive field strength at this location, in particular on account of the very small surface areas in the interconnect layer 5. These electrical field peaks produced by the charging effect described above cause a mixture of abrasive material and abraded metal, which is usually electrically conductive, formed during the planarization step to accumulate at these electrostatically charged interconnect layers 5 and/or to induce the formation of what are known as dendrites.
This growth and/or this accumulation of grinding residues S (slurry) can only be removed with difficulty, in particular with tightly packed semiconductor circuits and very small surface areas of the planarized interconnect layer 5, and consequently undesirable short circuits can occur with adjacent interconnect structures, or in the encapsulated state corrosion and degradation may propagate from this corrosive soiling.
FIGS. 2A and 2B show a simplified plan view and a simplified sectional view of a semiconductor circuit arrangement in accordance with the prior art in which this problem of the formation of dendrites and/or the accumulation of abrasive material S is eliminated.
In accordance with FIGS. 2A and 2B, this problem of dendrite formation in an integrated semiconductor circuit is usually eliminated by corresponding planarized interconnect layers or interconnect layers which are to be planarized being blunted by increasing their surface area and thereby reducing the electrical field strength in this region. More specifically, in accordance with FIGS. 2A and 2B, in the event of dendrite formation of this nature being detected, layout changes are usually made to the interconnect or metallization plane such that these very small interconnect surface areas 5 are correspondingly increased in size, with the result that the electrical field peaks in this region are sufficiently reduced and the above-described dendrite formation and/or the accumulation of grinding residues can be reliably prevented.
However, a drawback in this case is that the advantage of a higher integration density which is actually sought after is in this way at least partially negated again, since to avoid the formation of dendrites a metallization or interconnect surface area which is up to six times larger is required for each metallization or interconnect plane.
This in turn has adverse effects on the circuit design and on corrections to existing layouts, and consequently existing layouts cannot readily be converted to the next shrink down or the next integration density down.